In general, data can be stored as charge in a cell capacitor of a DRAM device and the stored charge can be lost in various ways. Accordingly, a refresh operation for periodically restoring information is typically required. The refresh time interval, which is the interval between consecutive refresh operations, can be enhanced by increasing the capacitance of the cell capacitor so that a larger amount of charge (Q) can be stored therein.
One method for increasing the capacitance of a cell capacitor is to use a ferroelectric material having a high dielectric coefficient as a dielectric layer of a capacitor. An interlayer dielectric layer is then formed on the entire surface of the capacitor including the ferroelectric material as the dielectric layer. The interlayer dielectric layer may comprise silicon dioxide. However, silicon dioxide may chemically react with the ferroelectric material and cause a deterioration in the characteristics of the capacitor. The reaction may also generate cracks in the silicon dioxide layer.
A method for preventing the above-described problems by preventing diffusion of the ferroelectric material and penetration of hydrogen into the ferroelectric material is disclosed in U.S. Pat. No. 5,212,620. In the '620 patent, a TiO.sub.2 layer is provided as a buffer layer between the ferroelectric material and the silicon dioxide interlayer dielectric layer. According to the '620 patent, a titanium (Ti) layer is formed and then treated at 650.degree. C. under an oxygen atmosphere, to thereby form a TiO.sub.2 layer. At this time, if the heat treatment is carried out at 650.degree. C. or less, the Ti layer may be incompletely oxidized to TiO or TiO.sub.x. The incompletely oxidized buffer layer may also have a low resistivity, and this may lead to an increase in leakage current between upper and lower electrodes of the capacitor. Also, a TiO.sub.2 layer formed by sputtering typically has low step coverage. However, in order to provide sufficiently small contact resistance between a contact plug and the lower electrode of the capacitor, any back-end processing steps typically must be performed at 650.degree. C. or lower. For example, if a subsequent process step is performed at 650.degree. C. or more, a barrier metal layer (for preventing diffusion of a lower electrode material into the contact plug) may be adversely affected and may not be able to function satisfactorily as a diffusion barrier layer. Accordingly, the use of TiO.sub.2 buffer layers may be inappropriate in processes which require low temperatures on the order of 650.degree. C. or less.